Iterative Logic Arrays (ILAs) are widely used in many applications, e.g., general-purpose processors, digital signal processors, and embedded processors. Owing to the advanced VLSI technology, new defect mechanisms exist in the fabricated circuits. In order to ascertain the quality of manufactured products, the traditional single cell fault model is not sufficient. Therefore, more realistic fault models such as sequential fault models and delay fault models should also be adopted. A cell delay fault occurs if and only if an input transition cannot be propagated to the cell's output through a path in the cell in a specified clock period. It has been shown that all SIC (single input change) pairs of a circuit are sufficient to detect all robustly detectable path delay faults within the circuit. We extend the concept of SIC pairs for iterative logic arrays. We say that an ILA is C-testable for cell delay faults if it is possible to apply all SIC pairs of a cell to each cell of the array in such a way that the number of test pairs for the array is a constant. This is based on a novel fault model, called Realistic Sequential Cell Fault Model (RS-CFM). Necessary conditions for sending this test set to each cell in the array and propagating faulty effects to the primary outputs are derived. An efficient algorithm is also presented to obtain such a test sequence. We use the pipelined array multiplier as an example to illustrate our approach. The number of test pairs for completely testing of the array is only 84. Moreover, the hardware overhead to make it delay fault testable is about 5.66%.

The EB tester line delay fault localization algorithm for combinational circuits is proposed where line delay fault probabilities are utilized to narrow fault candidates down to one efficiently. Probabilities for two main causes of line delay faults, defects of contact/vias along interconnections and crosstalk, are estimated through layout analysis. The algorithm was applied to 8 kinds of ISCAS'85 benchmark circuits to evaluate its performance where the guided probe (GP) diagnosis was used as the reference method. The proposed method can cut the number of probed lines to about 30% in average compared with those for the GP method. The total fault localization time was 31% of the time for the GP method and was 6% less than that of our previous method where the fault list generated in concurrent fault simulation is utilized.

A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.

Testing for delay faults is very important in the verification of the timing behavior of digital circuits. When a circuit which is unable to operate at the desired clock speed is identified, it is necessary to locate the delay fault(s) affecting the circuit in order to remedy the situation. In this paper, we present a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. We first present the basic rules for deducing suspected faults based on the multiple gate delay fault assumption. Next, in order to improve diagnostic resolution, we introduce rules for deducing non-existent faults based on the fault-free responses at the primary outputs. Using these rules, we present the detailed method for diagnosing multiple delay faults based on paths sensitized by test-pairs generated for marginal delays and gate delay faults [7]. Finally, we present results obtained from experiments on the ISCAS '85 benchmark circuits. The experimental results show the effectiveness of our method.